1. Field of the Invention
The present invention relates to a large volume memory system, or, in more detail, a memory system without a mechanical operation section such as a magnetic disk memory, which, furthermore, is capable of providing high speed data transmission, and, in particular, to a memory system with a cascade-type cell structure which is a memory system of greatest volume for use in image processing.
2. Description of the Prior Art
Efforts for improving micromachining technology to upgrade storage capacity (degree of integration) of semiconductor memory chips are continuing, but there is a tendency for processing technology to become more and more complicated and for production costs to increase.
In order to eliminate these drawbacks, consideration is being given to memory systems with an improved degree of integration (wherein many memory cells can be formed within a chip), with the processing technology remaining at the conventional level.
A conventional memory cell with this configuration is referred to as a cascade-type or a NAND cell type because a memory cell and a data transfer gate are normally used in parallel.
A memory cells of the cascade-gate-type cell (CGC) structure has a plurality of capacitors for storing data items and a plurality of MOS transistors. Each capacitor is located between each adjacent transistor pair for storing data. Each MOS transistor (a gate) is connected to each word line. A predetermined number of capacitors are connected in series and one end of the capacitors is connected to a bit line. The predetermined number of the capacitors are divided into a memory cell group. The memory cell group is called as the memory cell having the cascade-gate-type cell structure.
A memory cell structure in this type of memory system is hereinafter referred to as "cascade-type cell structure".
A memory system formed from memory cells with this cascade-type cell structure has the special feature of improved density of memory cells (degree of integration) whereby it is possible to arrange and localize the grouping of a specified number of memory cells within a chip. Accordingly, it is possible to provide a memory system with the same degree of integration (memory volume) as a memory cell of a structure wherein the memory cells and data transfer gates are consolidated, in about 60% of the area.
Next, the sense operation and restore operation will be explained for data in a conventional memory system with a cascade-type cell structure.
in FIG. 1, four word lines W1, W2, W3, W4 are provided as gates for reading out memory cell data to a bit line Bi for sixteen memory cells (141, 142, . . . , 1416), connected in a cascade configuration. The word lines (W1, W2, W3, W4) are opened (activated) successively from the side near to the bit line Bi. For example, when the word line W1 is activated the four memory cells (141, 142, 143, 144) are accessed in order and a reading or writing operation is performed for the data.
Data which has been read out of the memory cell must be temporarily stored in some location until the data is restored to that memory cell. For the reason, restore registers( r1, r2, r3, r4) are provided to store the data.
A data store operation and a refresh operation for the memory cell are carried out in the reverse order to the order in which the memory cell data is temporarily written into and read out of the restore register, by rewriting the data once again into that memory cell.
In the conventional memory system with a cascade-type cell structure shown in FIG. 1, sense amplifiers (S/A) are provided in the ratio of one to every four bit lines (b1, b2, b3, b4) to repeat the arrangement of the sense amplifiers (S/A) and to relive congestion of the pitch.
For this reason, selection transfer gates (G1 G2, G3, G4) are provided to select which memory cell group in one group of memory cell arrays (for example, the memory cells 141, 145, 149, 1413 are respectively cascade-connected and form one group) is to be connected to the sense amplifier (S/A).
Accordingly, sixteen memory cells (141, 142, . . . , 1416) can be considered as one lot in the memory cell read-out operation and the restore operation.
For example, when the data is read out of the deepest (furthest back) memory cell (for example, among the four cascade connected memory cells 141, 145, 149, 1413, the memory cell 1413 is the deepest), the data in the memory cells 141, 145, 149 is destroyed. Accordingly, prior to destruction, all the data in these memory cells must be sensed and that data temporarily saved in a restore register.
Next, after the data in the memory cell 1413 is read out, a restore operation must be performed for the memory cells 141, 145, 149 corresponding to the data temporarily saved in the restore register. This restore operation is identical to the read-out operation inasmuch as the data stored in the register is sensed and the result is transferred to the corresponding memory cell. Specifically, the word lines W1, W2, W3, W4 are activated in the opposite order to the read-out.
Accordingly, there is the problem in the conventional read-out operation of the cascade-type synchronous memory cell that the amount of time required for data transmission during a read-out operation in the cascade-type memory cell changes according to which memory cell the data is read from, because the number of sensing operations differs. In other words, there is a difference in the required number of sensing operations before the read-out from the memory cell to be accessed is started.
For this reason, there is the problem that the time necessary for data transmission to each memory cell changes. In this manner, in a conventional memory system with a cascade-type cell structure, there is a wide variation in the amount of time necessary for each data transmission so there is the problem that data access control is complicated. However, on the other hand, there is the advantage that the production cost of a memory cell with a cascade-type configuration is low, therefore a memory system giving these special features must be provided.
In addition, in a conventional memory system with a cascade-type cell structure, the control clock signal for supplying an address and the control clock signal for transmitting data from the memory cell to an external destination are separate signals. For this reason, there is the problem that control of the timing of the operation is complicated. In addition, a microprocessor (a CPU or the like) must supervise the timing until a row selection signal (RAS) is entered and data transmission from the memory cell is commenced. During this time the CPU cannot perform another process, resulting in poor efficiency.